Verilog On Linux: Defenestrating Modelsim

This tutorial’s to the victims of the Modelsim user experience, forced to design hardware in chains and gracefully handle the precious rear end of the popular musty racehorse that’s Mentor Graphics’ stable-star. If you’re on Linux, freedom’s a nice option.

Defenestrate /diˈfɛnəˌstreɪt/ (verb) : to throw (a person or thing) out of a window. The word originated from a couple of incidents in Prague, back in the 14th century, when a bunch of guys stormed in and tossed seven town officials out the window (quite literally).

I’ll walk you through the steps to start coding in Verilog on your Linux box:

  1. Install Icarus Verilog Simulator and GTKWave
  2. sudo apt-get install verilog gtkwave
  3. Copy this sample code and save it as counter.v:
  4. module counter(out, clk, reset);
    
      parameter WIDTH = 8;
    
      output [WIDTH-1 : 0] out;
      input            clk, reset;
    
      reg [WIDTH-1 : 0]   out;
      wire            clk, reset;
    
      always @(posedge clk)
        out <= out + 1;
    
      always @reset
        if (reset)
          assign out = 0;
        else
          deassign out;
    
    endmodule // counter
  5. Copy this sample code and save it as counter_tb.v
  6. module test;
    
     /* Make a reset that pulses once. */
     reg reset = 0;
     initial begin
     $dumpfile("test.vcd");
     $dumpvars(0,test);
    
     # 17 reset = 1;
     # 11 reset = 0;
     # 29 reset = 1;
     # 5  reset =0;
     # 513 $finish;
     end
    
     /* Make a regular pulsing clock. */
     reg clk = 0;
     always #1 clk = !clk;
    
     wire [7:0] value;
     counter c1 (value, clk, reset);
    
     initial
     $monitor("At time %t, value = %h (%0d)",
     $time, value, value);
    endmodule // test
    
  7. Open a terminal in the same directory and compile the code with this command:
  8. iverilog -o dsn counter_tb.v counter.v
  9. Run the code with this command:
  10. vvp dsn
  11. Simulate the generated output with this:
  12. gtkwave test.vcd &

    Expand test on the top-left panel and select c1, then drag the signals from the bottom-left (wire, reg) to the Signals panel to it’s immediate right. This should get you out on the right side of the bed with Verilog on Linux. Your next steps lie here. All sample code and instructions are merely distilled from the extensive documentation at the wiki linked to above. Cheers!

One response to “Verilog On Linux: Defenestrating Modelsim

  1. I keep referring to this post over and over again while using verilog on Linux!
    Regarding the .vcd file, a small module has to be inserted inside the testbench to generate it. The contents of the module can be found on the iverilog website.
    Its an amazing alternative for Xilinx and Modelsim! Thanks!

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